A low bandwidth signal may be sampled using a “fast” analog to digital converter (ADC). In such cases, the ADC may be configured to go into a low power mode between each conversion (i.e., sampling time plus associated conversion processing).
For example, shown in FIG. 1 is an exemplary waveform 100. At times 102a, 102b, it is desired to begin sampling the signal 100. Sampling occurs over a conversion time denoted by reference numerals 104a, 104b. During the period 106 between the end of conversion period 104a and the start of conversion time 104b, it may be desired to put the ADC into a low power mode.
However, exiting the low power mode, i.e., powering up, requires a time period that must be accounted for to ensure the accuracy of the ADC.